The present disclosure relates generally to the field of microelectronics. More specifically, the present disclosure is related to bit error rate testing of high speed devices with a substantial duty cycle distortion of an output signal (relative to the size of a bit period).
High-speed data communications requirements have prompted the development of devices, such as serializer/deserializer (Serdes) chips, that can send and receive data over a parallel link, thus transferring data at high Gigabit rates. Signal jitters or duty cycle distortion of the output signal of such devices, because of their high speed, can account for a substantial portion of a bit period. Accordingly, it can be a challenge to test such devices using automated test equipment (“ATE”). As a result, a bit error rate test on such a device must often be performed using equipment external to the ATE. The use of such external bit error rate testers, however, can be costly and time-consuming, especially for high-volume manufacturing facilities.